1. Field of Invention
The present invention relates generally to a method of fabricating an integrated circuit. More particularly the use of dummy lines to commonize the percentage of raised areas exposed during a spin-on glass etchback process is disclosed to reduce variations in the spin-on glass etchback process during fabrication.
2. Description of the Prior Art
Maintaining the planarity of a semiconductor wafer surface during the process of multilevel metallization is crucial to insure that there is no accidental coupling of active conductive traces between different layers of active conductive traces on integrated circuits housed on the wafer, and further to provide a surface with a constant height for any subsequent lithography processes. There are many processes which are intended to improve the planarity of a wafer surface during fabrication.
Spin-on glass (SOG) etchback is one process commonly used to improve the local planarity of a semiconductor wafer surface during the process of multilevel metallization. In the SOG etchback process, a layer of SOG is deposited over an insulating layer on the surface of a semiconductor wafer in order to fill in any gaps between metal lines on a trace layer of the wafer. Filling in the gaps between metal lines with SOG results in a planar surface on the wafer. The SOG layer is then etched back to remove all of the SOG over underlying metal lines where vias could be placed. The effectiveness of SOG etchback is dependent on the underlying pattern of metal lines and spaces on the surface of a semiconductor wafer.
FIGS. 1 and 2 are diagrammatic side views of a semiconductor wafer substrate 100 on which metal lines 112, 114, 116 are situated on a trace layer 120. The metal lines 112, 114, 116 are typically active conductive traces. In FIG. 1, an oxide layer 118 is deposited over the metal lines 112, 114, 116. The portions of the oxide layer 118 directly over the metal lines 112, 114, 116 appear raised with respect to the portions of the oxide layer 118 that do not directly overlie the metal lines 112, 114, 116 and are referred to herein as raised oxide areas 122. A layer of SOG 130 is then deposited over the oxide layer 118. FIG. 2 shows the surface of the substrate 100 after a SOG etchback process has occurred. The SOG layer 130 has been etched back to expose portions of the oxide layer 118 over the metal lines 112, 114, 116.
The local planarity of a semiconductor wafer surface has been observed to be very sensitive to the amount of SOG etched back during the SOG etchback process. For Application Specific Integrated Circuit (ASIC) products, the density of metal lines commonly varies from level to level on a single integrated circuit, as well as from product to product. This variation impacts the amount of the insulating layer, which is typically an oxide layer, exposed during SOG etchback, resulting in a variation in the micro-loading during etch. The micro-loading during etch is best described as the enhancement of the SOG etch rate which occurs when oxide exposed during the SOG etchback process affects the etch rate of the SOG adjacent to it. If the pattern density of the topography on a layer of a semiconductor wafer is uneven, the SOG and the oxide may be etched at different rates, thereby causing variations in the micro-loading during etch. Variations in the micro-loading during etch may result in wide variations in the planarity of a layer of a semiconductor wafer. It follows that the micro-loading during etch for layers of wafers with different pattern densities of topography will almost certainly not be the same.
In order to reduce variations in the micro-loading during etch, the SOG etchback process is occasionally modified before each layer of each product undergoes the process. By way of example, the gas flows and the amount of chemicals used during the SOG etchback process may be altered for each layer which is subjected to a SOG etchback process. From a manufacturability standpoint, however, changing the SOG etchback process for each product is far from ideal as it is both time-consuming and expensive.
While the use of a SOG coating and a SOG etchback process have been shown to be effective in improving the local planarity of the surface of a semiconductor wafer during fabrication, the development of an efficient, inexpensive method which would enable a common SOG etchback process to be used for an array of semiconductor products, without compromising the planarity of any of the layers on any of the products, is desirable.